1. Field of the Invention
This invention relates to a static RAM (SRAM) which employs a dynamic circuit for pre-charging and discharging a bit line and a processing apparatus which includes a static RAM of the type mentioned, and more particularly to a static RAM and a processing apparatus which are suitably used with an associative storage circuit represented by a tag RAM circuit of a cache memory system of the direct mapping type, the set associative mapping type or a like type.
2. Description of the Related Art
An exemplary one of ordinary processing apparatus which employ a static RAM is shown in FIG. 13. Referring to FIG. 13, the processing apparatus shown includes a pair of static RAMs (which may be hereinafter referred to as SRAMs) 50A and 50B. Each of the SRAMs 50A and 50B is of the n-bit x m-entry type and is shown employing a dynamic circuit for pre-charging and discharging bit lines.
The processing apparatus further includes a pair of flip-flops (FF) 51A and 51B for fetching and temporarily storing data di(0:n) (n bits from 0 to n-1) to be written into the SRAMs 50A and 50B in response to a clock signal and outputting the stored data di(0:n), respectively, a pair of decoders (DEC) 52A and 52B for the SRAMs 50A and 50B, respectively, and a pair of flip-flop apparatus (FF) 53A and 53B for fetching and temporarily storing data do(0:n) outputted from the SRAMs 50A and 50B in response to the clock signal and outputting the stored data do(0:n), respectively.
The processing apparatus further includes a pair of parity check circuits (PCHK) 54A and 54B for checking parity of data outputted from the SRAMs 50A and 50B, respectively, a comparison circuit (CMP) 55 for comparing data outputted from the SRAMs 50A and 50B to check whether or not they coincide with each other, a pair of flip-flops (FF) 56A and 56B for fetching and temporarily storing results pchk of parity checks from the parity check circuits 54A and 54B in response to the clock signal and outputting the stored parity check results pchk, respectively, and a flip-flop (FF) 57 for fetching and temporarily storing a result of comparison (active low) from the comparison circuit 55 in response to the clock signal and outputting the stored comparison result. The processing apparatus further includes an inverter 58 for inverting an active-low pre-charge signal for pre-charging bit lines of the SRAMs 50A and 50B and inputting the inverted pre-charge signal to the SRAMs 50A and 50B. A pre-charge period of the SRAMs 50A and 50B is offset by one half cycle from a pre-charge period of the other components.
With the ordinary processing apparatus, irrespective of whether or not a dynamic circuit is used for the SRAMs 50A and 50B, only a static output of a kept level is normally used as an output of the processing apparatus.
The processing apparatus described above with reference to FIG. 13 is used, for example, to check a tag of a cache memory (not shown) of the direct mapping type, that is, to determine whether or not data of a requested address is stored in the cache memory (hit/miss). For example, tag information of the cache memory (part of address information of data stored in the cache memory) is stored in the SRAM 50A while a physical address of the requested address is stored into the SRAM 50B. In other words, the SRAM 50B functions as a physical address storage section of an address translation buffer (TLB: Translation Look-aside Buffer).
When data are outputted from the SRAMs 50A and 50B, parity checks of the data are performed by the parity check circuits 54A and 54B, respectively, and address information from the SRAMs 50A and 50B is compared with each other by the comparison circuit 55. If coincidence is detected as a result of the comparison, the comparison circuit 55 determines this as a cache hit and outputs a hit signal. Consequently, the cache memory is accessed in accordance with the address information from the SRAM 50A or 50B stored in the flip-flop apparatus 53A or 53B so that data are read out from the cache memory.
The timings of such operations of the processing apparatus as described above are illustrated in FIG. 14. Referring to FIG. 14, if the SRAMs 50A and 50B are accessed for reading at a timing T1 at which the clock signal clk rises, then data (address information) corresponding to the reading accessing are outputted from the SRAMs 50A and 50B at a next timing T2. Then at a further timing T3, the data outputs from the SRAMs 50A and 50B are compared with each other by the comparison circuit 55, and a result cmp of the comparison is stored into the flip-flop 57. Thereafter, at a next timing T4 at which the clock signal clk rises, the comparison result cmp is outputted as cache hit/miss information from the flip-flop 57.
With the ordinary processing apparatus which includes the SRAMs 50A and 50B described above, however, since the SRAMs 50A and 50B output only static outputs of kept levels irrespective of whether or not a dynamic circuit is used for the SRAMs 50A and 50B, there is a problem to be solved in that a delay time after which data read out from a RAM cell appears by way of a sense amplifier (differential amplifier) and a level keeping circuit provides a severe restriction to the propagation delay time/setup time and the number of stages of gates of any circuit (such as the parity check circuit 54A or 54B or the comparison circuit 55) which receives the output data.
Further, since the conventional SRAMs 50A and 50B include only one kind of output lines (do(0:n) in FIG. 13) of a kept level, the load such as the number of gates and/or wiring lines connected to the output lines is accordingly great, and this provides a corresponding long delay time. Consequently, more severe timings are required for a system for which a shorter clock cycle and a higher speed operation are required.